1. Field of Invention
The present invention relates to a method of fabricating an integrated circuit. More particularly the invention relates to the use of directed radiation to selectively heat the surface of a semiconductor substrate between metal traces and thereby selectively deposit a dielectric layer between the metal traces during fabrication, forming a flat surface for further processing.
2. Description of the Prior Art
Maintaining the planarity of a semiconductor wafer surface during the process of multilevel metallization is crucial to insure that there is no accidental coupling of metal traces between different metallization layers of integrated circuits housed on the wafer, and further to provide a surface with a sufficient planarity for any subsequent optical lithography processes. There are many processes which are intended to improve the planarity of a wafer surface during fabrication.
Spin-on glass (SOG) etchback is one process commonly used to improve the planarity of a semiconductor wafer surface during the process of multilevel metallization. In the SOG etchback process, a layer of SOG is deposited over a dielectric layer on the surface of a semiconductor wafer in order to fill in any gaps between metal lines on a trace layer of the wafer. Typically, filling in the gaps between metal traces with SOG results in a planar surface on the wafer. The SOG layer is then etched back to remove all of the SOG over underlying metal traces where vias are to be placed.
The effectiveness of SOG etchback is dependent upon the underlying pattern of metal traces and gaps on a trace layer of a semiconductor wafer. For example, it has been observed that if the gaps between the metal traces are too small, voids form in the dielectric material. Once the SOG layer is etched back, the voids in the dielectric layer may be exposed, thereby compromising the global planarity of the surface of the semiconductor wafer.
A Chemical Mechanical Polishing (CMP) process is another process which is commonly used to improve planarity on the surface of a semiconductor wafer. The CMP process is implemented after a dielectric material has been deposited over a metallization layer of a semiconductor wafer. A typical CMP process involves the use of a polishing pad, made from a synthetic material, and a polishing slurry. Semiconductor wafers are mounted on a polishing fixture such that the wafers are pressed against the polishing pad under high pressure. The fixture then rotates and translates the wafers relative to the polishing pad. Wafer polishing is accomplished when the heat generated by friction between the wafer and the polishing pad causes the oxidization of some of the chemicals which comprise a dielectric layer of the wafer. Particles in the polishing slurry then abrade the oxidized chemicals away, thereby polishing the wafer.
Although the CMP process has been observed to be effective in planarizing the surfaces of semiconductor wafers, variations in planarity may still occur on wafer surfaces if the topographies of the underlying surfaces are very uneven. Further, if the gaps between adjacent metal traces are not sufficiently filled, the CMP process will not be able to planarize the surface of the wafer.
The SOG etchback and CMP procedures may add considerable cost to an integrated circuit. Both procedures require that a wafer be transferred to specialized apparatus that performs only planarization steps. The SOG etchback process requires one piece of apparatus for "spinning on" the glass and another piece of apparatus for plasma etching the glass on the wafer. The CMP process requires a special wafer platen, a polishing pad, and a chemical dispensing system. If the excess costs associated with these procedures could be reduced or eliminated, the cost of producing integrated circuits could be reduced.
FIGS. 1a and 1b are diagrammatic side views of semiconductor wafer substrates on which metal traces are situated. In FIG. 1a, the metal traces 110 are situated on a semiconductor wafer substrate 100. A coating of a dielectric material 120 is deposited over the traces 110. The metal traces 110 are spaced such that it is possible for an even coating of a dielectric material 120 to be deposited. In FIG. 1b, the metal traces 180 situated on a semiconductor substrate 160 are spaced such that there is a relatively small gap between metal traces 180b and 180c. This relatively small gap between metal traces 180b and 180c causes a void 185 to be created in the dielectric material 190 when it is deposited over the traces 180a-180f. This void 185 compromises the integrity of the layer of dielectric material 190 in that it creates a vacuum in the layer of dielectric material 190.
Although both a SOG etchback process and a CMP process have been shown to improve the planarity of semiconductor wafers, the effectiveness of both processes is largely affected by the gap-fill capabilities of dielectric materials deposited over metal traces on a trace layer of a wafer. As described above, common methods for depositing dielectric materials over a trace layer of a wafer do not serve to sufficiently fill small gaps with dielectric material. The development of a method for depositing dielectric material which can evenly fill gaps of any size between metal traces on a trace layer would greatly improve the effectiveness of processes, as for example the SOG etchback process and the CMP process previously described, intended to achieve planarity on the surface of a wafer during fabrication. Such a method may even make it possible to achieve a planar surface on a wafer without the need for costly and time-consuming processes like SOG etchback and CMP.